1. Field of the Invention
The present invention relates in general to an integrated circuit including capacitors. In particular, the present invention relates to capacitors with damascene structures and method for forming the same.
2. Description of the Related Art
Capacitors are deployed in various integrated circuits. For example, capacitors can be used as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution. Capacitors also have wide applications in analog/logic, analog-to-digital, mixed signal, radio frequency circuits and so on.
A conventional method of manufacturing a semiconductor apparatus including a capacitor 20 formed of metal-insulator-metal layers is described with reference to FIGS. 1Axcx9c1D. As shown in FIG. 1A, an aluminum layer is deposited on an insulator 12 which contains interconnections and is formed on a silicon substrate having devices (not shown) thereon and therein. The aluminum layer is then patterned by masking and etching to form wires 14a and 14b. As shown in FIG. 1B, an insulator 16 with a tungsten plug 18 (hereafter xe2x80x9cW-plugxe2x80x9d) used to connect the aluminum wire 14a and the to-be-formed capacitor is formed on the aluminum wires 14a and 14b and the insulator 12. As shown in FIG. 1C, a first conductive plate 21, a dielectric layer 22 and a second conductive plate 23 are sequentially deposited on the insulator 16 and the W-plug 18, and then patterned by masking and etching to obtain a capacitor 20. The first conductive plate 21, the bottom electrode, is connected with the aluminum wire 14a through the W-plug 18. Another insulator 26 is deposited on the insulator 16 and the capacitor 20. The insulators 16 and 26 are patterned and W-plug 28a and W-plug 28b are formed therein. As shown in FIG. 1D, an aluminum layer (not shown) is deposited on the insulator 26 and the W-plugs 28a and 28b. The aluminum layer is then patterned by masking and etching to form wires 34a and 34b. The aluminum wire 34a is connected with the second conductive plate 23 through the W-plug 28a. The aluminum wire 34b is connected with the aluminum wire 14b through the W-plug 28b. 
This method for integrating the capacitor 20 into an integrated circuit requires several masking and etching steps to form the capacitor 20, which may increase overall fabrication costs. Moreover, if a greater capacitance of the plane capacitor 20 is required, a greater area of the plane capacitor 20 is needed. This will sacrifice the spaces between the capacitor 20 and the nearby wires and make scaling down difficult. Furthermore, a drop height exists between the capacitor area and the non-capacitor area, resulting in an uneven topography of the insulator 26.
A method of manufacturing a capacitor while simultaneously forming a dual damascene via is disclosed in U.S. Pat. No. 6,025,226. In the ""226 patent, a conductor which is used to form a bottom electrode is deposited in the openings for the via and capacitor. However, the conductor should be sufficiently thick to fill the via opening and sufficiently thin to not planarize the capacitor opening. It is difficult to form such a conductor.
Besides, the aluminum used to fabricate the traditional interconnections cannot satisfy the trends of enhanced integration and speed of data transmission. Copper (Cu) has high electric conductivity to reduce RC delay and can be substituted for aluminum as conducting wires. The use of copper as the conducting wires requires the use of processes, that is, damascene processes, because copper cannot be patterned by etching processes. This is because the boiling point of copper chloride (CuCl2) produced by copper and the chlorine plasma usually used to etch metal is relatively high, about 1500xc2x0 C. Therefore, Cu processes should be used to fabricate an integrated circuit including a capacitor.
It is an object of the present invention to provide a method for forming metal capacitors with a damascene process.
It is another object of the invention to reduce the number of masking and etching steps in manufacturing an integrated circuit including a capacitor.
Yet another object of the invention is to reduce the cost of manufacturing an integrated circuit including a capacitor.
It is a further object of the invention to reduce the drop height existing between the capacitor area and the non-capacitor area.
Still another object of the invention is to provide easily controllable processes of manufacturing an integrated circuit including a capacitor.
Another object of the invention is to use the Cu processes to fabricate the integrated circuit including capacitors to reduce RC delay.
Another object of the invention is to provide metal capacitors with damascene structures.
The present invention provides a metal capacitor with damascene structures. A first Cu wire and a second Cu wire are disposed in a first insulator. A second insulator with an opening is disposed on the first insulator, wherein the opening is positioned on the first Cu wire. A stop layer is disposed on the second insulator, and the opening in the second insulator is extended to the stop layer. A first metal layer is conformally disposed in the opening and contacts the surface of the first Cu wire. A dielectric layer is conformally disposed on the first metal layer in the opening. A second metal layer is conformally disposed on the dielectric layer in the opening. A third insulator is disposed on the stop layer and the second metal layer. A first Cu damascene structure and a second Cu damascene structure are disposed in the second and third insulators and the stop layer, wherein the first Cu damascene structure is composed of a third Cu wire and a first Cu plug and the second Cu damascene structure is composed of a fourth Cu wire and a second Cu plug, wherein the second metal layer is connected with the third Cu wire through the first Cu plug, and the fourth Cu wire is connected with the second Cu wire through the second Cu plug. A first sealing layer is disposed between the second Cu wire and the second insulator. A second sealing layer is disposed on the third and fourth Cu wires.
The present invention provides a method for forming the above-mentioned metal capacitor with a damascene process. Before fabricating the thin-film capacitor, a first Cu wire and a second Cu wire, surrounded with a barrier layer and a first sealing layer, are prepared in a first insulator. A second insulator is formed on the sealing layer. A stop layer is formed on the second insulator. An opening is formed in the stop layer, the second insulator and the sealing layer and the first Cu wire is exposed. A first metal layer, a third insulator and a second metal layer are conformally formed, in turn, in the opening on the stop layer. A chemical mechanical polishing process is executed to remove the first metal layer, the third insulator and the second metal layer until the stop layer is exposed; thereby, a bottom electrode, a capacitor dielectric and an upper electrode are formed in the opening respectively. The bottom electrode is connected to the first Cu wire. A fourth insulator having dual damascene structures is formed over the capacitor and the stop layer.